FIGS. 9(a)-9(i) are sectional views illustrating process steps in a method for producing a field effect transistor (hereinafter, referred to as an FET) having a double-stage recess according to the prior art.
Initially, in the step of FIG. 9(a), an n type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1 by epitaxial growth, and then a prescribed portion of the n type GaAs layer 2 is etched to a prescribed depth by anisotropic dry etching or wet etching to form a first stage recess 2a. Thereafter, an SiO film 4 is deposited over the entire surface of the wafer by plasma CVD, followed by patterning of a photoresist 5 on the SiO film 4.
In the step of FIG. 9(c), employing the photoresist pattern 5 as a mask, the SiO film 4 is selectively etched by reactive ion etching (RIE) and the n type GaAs layer 2 is selectively etched to a prescribed depth by anisotropic dry etching or wet etching to form a second stage recess 2b.
Thereafter, an SiO film 6 is deposited over the entire surface as shown in FIG. 9(d), and it is anisotropically etched to form side walls 6 on the both sides of the recess.
In the step of FIG. 9(f), WSi 7 and Au 8 are successively deposited over the surface of the structure by sputtering.
Next, in the step of FIG. 9(g), using a photoresist mask (not shown), Au 8 and WSi 7 are successively etched by ion-milling and RIE with a gas mixture of CF.sub.4 and O.sub.2, respectively.
Thereafter, the SiO film 4 and the side walls 6 are removed as shown in FIG. 9(h).
Finally, in the step of FIG. 9(i), source and drain electrodes 9 are formed to complete a semiconductor device.
In the prior art method, after patterning of the first stage recess 2a, the second stage recess 2b is patterned in the first stage recess 2a, so that mask alignment must be performed twice.
In the prior art double recess type FET, since the first and second stage recesses are formed using different masks, so mask alignment must be performed twice. Therefore, misalignment of the masks occurs, whereby the widths of the first stage recess and the second stage recess are different from design widths and vary from wafer to wafer.